Datasheet
V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 316 of 870
Sep 30, 2010
Figure 8-17. Basic Timing in External Trigger Pulse Output Mode
D
1
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3
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1
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3
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1
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2
D
3
D
1
D
1
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3
Active level
width (D
2
)
Active level
width (D
2
)
Active level
width (D
2
)
Active level
width (D
3
)
Active level
width (D
3
)
Cycle (D
0
+ 1) Cycle (D
0
+ 1)Wait
for trigger
Active level
width (D
3
)
Cycle (D
0
+ 1)
FFFFH
16-bit counter
0000H
TQ0CE bit
External trigger input
(TIQ00 pin input)
TQ0CCR0 register
INTTQ0CC0 signal
TOQ00 pin output
(only when software
trigger is used)
TQ0CCR1 register
INTTQ0CC1 signal
TOQ01 pin output
TQ0CCR2 register
INTTQ0CC2 signal
TOQ02 pin output
TQ0CCR3 register
INTTQ0CC3 signal
TOQ03 pin output
Active level
width
(D
1
)
Active level
width
(D
1
)
Active level
width
(D
1
)
Active level
width
(D
1
)
Active level
width
(D
1
)
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0
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1
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3
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2
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0
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0
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D
0
16-bit timer/event counter Q waits for a trigger when the TQ0CE bit is set to 1. When the trigger is generated, the 16-bit
counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOQ0k