Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 315 of 870
Sep 30, 2010
8.5.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010)
In the external trigger pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit
is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter Q starts counting,
and outputs a PWM waveform from the TOQ01 to TOQ03 pins.
Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software
trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOQ00 pin.
Figure 8-16. Configuration in External Trigger Pulse Output Mode
CCR0 buffer register
TQ0CE bit
TQ0CCR0 register
Clear
Match signal
INTTQ0CC0 signal
TOQ03 pin
INTTQ0CC3 signal
TOQ00 pin
TIQ00 pin
Transfer
S
R
TQ0CCR1
register
CCR1 buffer
register
Match signal
TOQ01 pin
INTTQ0CC1 signal
Transfer
Transfer
S
R
TQ0CCR3
register
CCR3 buffer
register
Match signal
Transfer
TOQ02 pin
INTTQ0CC2 signal
S
R
TQ0CCR2
register
CCR2 buffer
register
Match signal
16-bit counter
Count
clock
selection
Count
start
control
Edge
detector
Software trigger
generation
Output
controller
(RS-FF)
Output
controller
Output
controller
(RS-FF)
Output
controller