Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 311 of 870
Sep 30, 2010
(b) Notes on rewriting the TQ0CCR0 register
To change the value of the TQ0CCR0 register to a smaller value, stop counting once and then change the set
value.
If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
16-bit counter
0000H
TQ0CE bit
TQ0CCR0 register
INTTQ0CC0 signal
D1 D2
D1 D1
D2D2 D2
External event
count signal
interval (1)
(D
1 + 1)
External event count signal
interval (NG)
(10000H + D
2 + 1)
External event
count signal
interval (2)
(D
2 + 1)
If the value of the TQ0CCR0 register is changed from D
1 to D2 while the count value is greater than D2 but less
than D1, the count value is transferred to the CCR0 buffer register as soon as the TQ0CCR0 register has been
rewritten. Consequently, the value that is compared with the 16-bit counter is D
2.
Because the count value has already exceeded D
2, however, the 16-bit counter counts up to FFFFH, overflows,
and then counts up again from 0000H. When the count value matches D2, the INTTQ0CC0 signal is generated.
Therefore, the INTTQ0CC0 signal may not be generated at the valid edge count of “(D
1 + 1) times” or “(D2 + 1)
times” originally expected, but may be generated at the valid edge count of “(10000H + D
2 + 1) times”.