Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 310 of 870
Sep 30, 2010
(2) Operation timing in external event count mode
Cautions 1. In the external event count mode, do not set the TQ0CCR0 register to 0000H.
2. In the external event count mode, use of the timer output is disabled. If performing timer
output using external event count input, set the interval timer mode, and select the operation
enabled by the external event count input for the count clock (TQ0CTL1.TQ0MD2 to
TQ0CTL1.TQ0MD0 bits = 000, TQ0CTL1.TQ0EEE bit = 1).
(a) Operation if TQ0CCR0 register is set to FFFFH
If the TQ0CCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the
external event count signal has been detected. The 16-bit counter is cleared to 0000H in synchronization with
the next count-up timing, and the INTTQ0CC0 signal is generated. At this time, the TQ0OPT0.TQ0OVF bit is
not set.
FFFFH
16-bit counter
0000H
TQ0CE bit
TQ0CCR0 register
INTTQ0CC0 signal
FFFFH
External event
count signal
interval
External event
count signal
interval
External event
count signal
interval