Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 307 of 870
Sep 30, 2010
When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
each time the valid edge of external event count input is detected. Additionally, the set value of the TQ0CCR0 register is
transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, and a compare match interrupt request signal (INTTQ0CC0) is generated.
The INTTQ0CC0 signal is generated each time the valid edge of the external event count input has been detected (set
value of TQ0CCR0 register + 1) times.
Figure 8-11. Register Setting for Operation in External Event Count Mode (1/2)
(a) TMQ0 control register 0 (TQ0CTL0)
0/1 0 0 0 0
TQ0CTL0
0: Stop counting
1: Enable counting
000
TQ0CKS2 TQ0CKS1 TQ0CKS0TQ0CE
(b) TMQ0 control register 1 (TQ0CTL1)
00000
TQ0CTL1
0, 0, 1:
External event count mode
001
TQ0MD2 TQ0MD1 TQ0MD0TQ0EEETQ0EST
(c) TMQ0 I/O control register 0 (TQ0IOC0)
00000
TQ0IOC0
0: Disable TOQ00 pin output
0: Disable TOQ01 pin output
000
TQ0OE1 TQ0OL0 TQ0OE0TQ0OL1
TQ0OE3 TQ0OL2 TQ0OE2TQ0OL3
0: Disable TOQ02 pin output
0: Disable TOQ03 pin output
(d) TMQ0 I/O control register 2 (TQ0IOC2)
0 0 0 0 0/1
TQ0IOC2
Select valid edge
of external event
count input
0/1 0 0
TQ0EES0 TQ0ETS1 TQ0ETS0TQ0EES1
(e) TMQ0 counter read buffer register (TQ0CNT)
The count value of the 16-bit counter can be read by reading the TQ0CNT register.