Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 306 of 870
Sep 30, 2010
8.5.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001)
In the external event count mode, the valid edge of the external event count input is counted when the
TQ0CTL0.TQ0CE bit is set to 1, and an interrupt request signal (INTTQ0CC0) is generated each time the specified
number of edges have been counted. The TOQ00 pin cannot be used.
Usually, the TQ0CCR1 to TQ0CCR3 registers are not used in the external event count mode.
Figure 8-9. Configuration in External Event Count Mode
16-bit counter
CCR0 buffer registerTQ0CE bit
TQ0CCR0 register
Edge
detector
Clear
Match signal
INTTQ0CC0 signal
TIQ00 pin
(external event
count input)
Figure 8-10. Basic Timing in External Event Count Mode
FFFFH
16-bit counter
0000H
TQ0CE bit
TQ0CCR0 register
INTTQ0CC0 signal
D 0
D 0 D 0 D 0
16-bit counter
TQ0CCR0 register
INTTQ0CC0 signal
External event
count input
(TIQ00 pin input)
D 0
External
event
count
interval
(D
0 + 1)
D 0 − 1D 0 0000 0001
External
event
count
interval
(D
0 + 1)
External
event
count
interval
(D
0 + 1)
Remark This figure shows the basic timing when the rising edge is specified as the valid edge of the
external event count input.