Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 304 of 870
Sep 30, 2010
If the set value of the TQ0CCRk register is less than the set value of the TQ0CCR0 register, the INTTQ0CCk
signal is generated once per cycle. At the same time, the output of the TOPQ0k pin is inverted.
The TOQ0k pin outputs a square wave with the same cycle as that output by the TOQ00 pin.
Remark k = 1 to 3
Figure 8-7. Timing Chart When D
01 ≥ Dk1
D 01
D 11
D 21
D 31
D 21
D 11
D 31
D 01 D 01
D 21
D 11
D 31
D 01
D 21
D 11
D 31
D 01
D 21
D 11
D 31
FFFFH
16-bit counter
0000H
TQ0CE bit
TQ0CCR0 register
TOQ00 pin output
INTTQ0CC0 signal
TQ0CCR1 register
TOQ01 pin output
INTTQ0CC1 signal
TQ0CCR2 register
TOQ02 pin output
INTTQ0CC2 signal
TQ0CCR3 register
TOQ03 pin output
INTTQ0CC3 signal