Datasheet
V850ES/JG3 CHAPTER 2 PIN FUNCTIONS
R01UH0015EJ0300 Rev.3.00 Page 16 of 870
Sep 30, 2010
(3/5)
Pin Name Pin No. I/O Function Alternate Function
INTP0 18 P03/ADTRG
INTP1 19 P04
INTP2 20 P05/DRST
INTP3 21 P06
INTP4 56 P913/A13
INTP5 57 P914/A14/TIP51/TOP51
INTP6 58 P915/A15/TIP50/TOP50
INTP7 26
Input
External interrupt request input (maskable, analog noise
elimination).
Analog noise elimination or digital noise elimination
selectable for INTP3 pin.
5 V tolerant.
P31/RXDA0/SIB4
KR0
Note 1
37 P50/TIQ01/TOQ01/RTP00
KR1
Note 1
38 P51/TIQ02/TOQ02/RTP01
KR2
Note 1
39
P52/TIQ03/TOQ03/
RTP02/DDI
KR3
Note 1
40
P53/SIB2/TIQ00/TOQ00/
RTP03/DDO
KR4
Note 1
41 P54/SOB2/RTP04/DCK
KR5
Note 1
42 P55/SCKB2/RTP05/DMS
KR6
Note 1
43 P90/A0/TXDA1/SDA02
KR7
Note 1
44
Input
Key interrupt input (on-chip analog noise eliminator).
5 V tolerant.
P91/A1/RXDA1/SCL02
NMI
Note 2
17 Input
External interrupt input (non-maskable, analog noise
elimination). 5 V tolerant.
P02
RD 67 Output Read strobe signal output for external memory PCT4
REGC 10
−
Connection of regulator output stabilization capacitance
(4.7
μ
F (recommended value))
−
RESET 14 Input System reset input
−
RTP00 37 P50/TIQ01/KR0/TOQ01
RTP01 38 P51/TIQ02/KR1/TOQ02
RTP02 39 P52/TIQ03/KR2/TOQ03/DDI
RTP03 40
P53/SIB2/KR3/TIQ00/TOQ00/
DDO
RTP04 41 P54/SOB2/KR4/DCK
RTP05 42
Output
Real-time output port.
N-ch open-drain output selectable.
5 V tolerant.
P55/SCKB2/KR5/DMS
RXDA0 26 P31/INTP7/SIB4
RXDA1 44 P91/A1/KR7/SCL02
RXDA2 36
Input
Serial receive data input (UARTA0 to UARTA2)
5 V tolerant.
P39/SCL00
SCKB0 24 P42
SCKB1 52 P99/A9
SCKB2 42 P55/KR5/RTP05/DMS
SCKB3 55 P912/A12
SCKB4 27
I/O
Serial clock I/O (CSIB0 to CSIB4)
N-ch open-drain output selectable.
5 V tolerant.
P32/ASCKA0/TIP00/TOP00
Notes 1. Pull this pin up externally.
2. The NMI pin alternately functions as the P02 pin. It functions as the P02 pin after reset. To enable the NMI pin,
set the PMC0.PMC02 bit to 1. The initial setting of the NMI pin is “No edge detected”. Select the NMI pin valid
edge using INTF0 and INTR0 registers.