Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 301 of 870
Sep 30, 2010
(2) Interval timer mode operation timing
(a) Operation if TQ0CCR0 register is set to 0000H
If the TQ0CCR0 register is set to 0000H, the INTTQ0CC0 signal is generated at each count clock subsequent
to the first count clock, and the output of the TOQ00 pin is inverted.
The value of the 16-bit counter is always 0000H.
Count clock
16-bit counter
TQ0CE bit
TQ0CCR0 register
TOQ00 pin output
INTTQ0CC0 signal
0000H
Interval time
Count clock cycle
Interval time
Count clock cycle
FFFFH 0000H 0000H 0000H 0000H
(b) Operation if TQ0CCR0 register is set to FFFFH
If the TQ0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to
0000H in synchronization with the next count-up timing. The INTTQ0CC0 signal is generated and the output of
the TOQ00 pin is inverted. At this time, an overflow interrupt request signal (INTTQ0OV) is not generated, nor
is the overflow flag (TQ0OPT0.TQ0OVF bit) set to 1.
FFFFH
16-bit counter
0000H
TQ0CE bit
TQ0CCR0 register
TOQ00 pin output
INTTQ0CC0 signal
FFFFH
Interval time
10000H ×
count clock cycle
Interval time
10000H ×
count clock cycle
Interval time
10000H ×
count clock cycle