Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 300 of 870
Sep 30, 2010
(1) Interval timer mode operation flow
Figure 8-5. Software Processing Flow in Interval Timer Mode
FFFFH
16-bit counter
0000H
TQ0CE bit
TQ0CCR0 register
TOQ00 pin output
INTTQ0CC0 signal
D0
D0 D0 D0
<1> <2>
TQ0CE bit = 1
TQ0CE bit = 0
Register initial setting
TQ0CTL0 register
(TQ0CKS0 to TQ0CKS2 bits)
TQ0CTL1 register,
TQ0IOC0 register,
TQ0CCR0 register
Initial setting of these registers is performed
before setting the TQ0CE bit to 1.
The TQ0CKS0 to TQ0CKS2 bits can be
set at the same time when counting has
been started (TQ0CE bit = 1).
The counter is initialized and counting is
stopped by clearing the TQ0CE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow