Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 299 of 870
Sep 30, 2010
Figure 8-4. Register Setting for Interval Timer Mode Operation (2/2)
(c) TMQ0 I/O control register 0 (TQ0IOC0)
0/1 0/1 0/1 0/1 0/1
TQ0IOC0
0: Disable TOQ00 pin output
1: Enable TOQ00 pin output
Setting of output level with
operation of TOQ00 pin disabled
0: Low level
1: High level
0: Disable TOQ01 pin output
1: Enable TOQ01 pin output
Setting of output level with
operation of TOQ01 pin disabled
0: Low level
1: High level
0/1 0/1 0/1
TQ0OE1 TQ0OL0 TQ0OE0TQ0OL1
0: Disable TOQ02 pin output
1: Enable TOQ02 pin output
Setting of output level with
operation of TOQ02 pin disabled
0: Low level
1: High level
0: Disable TOQ03 pin output
1: Enable TOQ03 pin output
Setting of output level with
operation of TOQ03 pin disabled
0: Low level
1: High level
TQ0OE3 TQ0OL2 TQ0OE2TQ0OL3
(d) TMQ0 counter read buffer register (TQ0CNT)
By reading the TQ0CNT register, the count value of the 16-bit counter can be read.
(e) TMQ0 capture/compare register 0 (TQ0CCR0)
If the TQ0CCR0 register is set to D
0, the interval is as follows.
Interval = (D
0 + 1) × Count clock cycle
(f) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3)
Usually, the TQ0CCR1 to TQ0CCR3 registers are not used in the interval timer mode. However, the set
value of the TQ0CCR1 to TQ0CCR3 registers are transferred to the CCR1 to CCR3 buffer registers. The
compare match interrupt request signals (INTTQ0CC1 to INTTQ0CCR3) is generated when the count
value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers.
Therefore, mask the interrupt request by using the corresponding interrupt mask flags (TQ0CCMK1 to
TQ0CCMK3).
Remark TMQ0 I/O control register 1 (TQ0IOC1), TMQ0 I/O control register 2 (TQ0IOC2), and TMQ0
option register 0 (TQ0OPT0) are not used in the interval timer mode.