Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 298 of 870
Sep 30, 2010
When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with
the count clock, and the counter starts counting. At this time, the output of the TOQ00 pin is inverted. Additionally, the set
value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, the output of the TOQ00 pin is inverted, and a compare match interrupt request signal (INTTQ0CC0) is
generated.
The interval can be calculated by the following expression.
Interval = (Set value of TQ0CCR0 register + 1) × Count clock cycle
Figure 8-4. Register Setting for Interval Timer Mode Operation (1/2)
(a) TMQ0 control register 0 (TQ0CTL0)
0/1 0 0 0 0
TQ0CTL0
Select count clock
0: Stop counting
1: Enable counting
0/1 0/1 0/1
TQ0CKS2 TQ0CKS1 TQ0CKS0TQ0CE
(b) TMQ0 control register 1 (TQ0CTL1)
0 0 0/1
Note
00
TQ0CTL1
0, 0, 0:
Interval timer mode
000
TQ0MD2 TQ0MD1 TQ0MD0TQ0EEETQ0EST
0: Operate on count
clock selected by bits
TQ0CKS0 to TQ0CKS2
1: Count with external
event count input signal
Note This bit can be set to 1 only when the interrupt request signals (INTTQ0CC0 and INTTQ0CCk) are masked
by the interrupt mask flags (TQ0CCMK0 to TQ0CCMKk) and the timer output (TOQ0k) is performed at the
same time. However, the TQ0CCR0 and TQ0CCRk registers must be set to the same value (see 8.5.1 (2)
(d) Operation of TQ0CCR1 to TQ0CCR3 registers) (k = 1 to 3).