Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 297 of 870
Sep 30, 2010
8.5.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000)
In the interval timer mode, an interrupt request signal (INTTQ0CC0) is generated at the specified interval if the
TQ0CTL0.TQ0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOQ00 pin.
Usually, the TQ0CCR1 to TQ0CCR3 registers are not used in the interval timer mode.
Figure 8-2. Configuration of Interval Timer
16-bit counter
Output
controller
CCR0 buffer registerTQ0CE bit
TQ0CCR0 register
Count clock
selection
Clear
Match signal
TOQ00 pin
INTTQ0CC0 signal
Figure 8-3. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
0000H
TQ0CE bit
TQ0CCR0 register
TOQ00 pin output
INTTQ0CC0 signal
D 0
D 0 D 0 D 0 D 0
Interval (D 0 + 1) Interval (D 0 + 1) Interval (D 0 + 1) Interval (D 0 + 1)