Datasheet

V850ES/JG3 CHAPTER 2 PIN FUNCTIONS
R01UH0015EJ0300 Rev.3.00 Page 15 of 870
Sep 30, 2010
(2/5)
Pin Name Pin No. I/O Function Alternate Function
ADTRG 18 Input A/D converter external trigger input. 5 V tolerant. P03/INTP0
ANI0 100 P70
ANI1 99 P71
ANI2 98 P72
ANI3 97 P73
ANI4 96 P74
ANI5 95 P75
ANI6 94 P76
ANI7 93 P77
ANI8 92 P78
ANI9 91 P79
ANI10 90 P710
ANI11 89
Input Analog voltage input for A/D converter
P711
ANO0 3 P10
ANO1 4
Output Analog voltage output for D/A converter
P11
ASCKA0 27 Input UARTA0 baud rate clock input. 5 V tolerant. P32/SCKB4/TIP00/TOP00
ASTB 68 Output Address strobe signal output for external memory PCT6
AVREF0 1
Reference voltage input for A/D converter/positive power
supply for port 7
−
AVREF1 5
−
Reference voltage input for D/A converter/positive power
supply for port 1
−
AVSS 2
−
Ground potential for A/D and D/A converters (same
potential as V
SS)
−
CLKOUT 62 Output Internal system clock output PCM1
DCK 41 Input Debug clock input. 5 V tolerant. P54/SOB2/KR4/RTP04
DDI 39 Input Debug data input. 5 V tolerant. P52/TIQ03/KR2/TOQ03/RTP02
DDO
Note
40 Output
Debug data output. N-ch open-drain output selectable.
5 V tolerant.
P53/SIB2/KR3/TIQ00/TOQ00/
RTP03
DMS 42 Input Debug mode select input. 5 V tolerant. P55/SCKB2/KR5/RTP05
DRST 20 Input Debug reset input. 5 V tolerant. P05/INTP2
EVDD 34, 70
−
Positive power supply for external (same potential as VDD)
−
EVSS 33, 69
−
Ground potential for external (same potential as VSS)
−
FLMD0 8
−
FLMD1 76
Input Flash memory programming mode setting pin
PDL5/AD5
HLDAK 63 Output Bus hold acknowledge output PCM2
HLDRQ 64 Input Bus hold request input PCM3
Note In the on-chip debug mode, high-level output is forcibly set.