Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 286 of 870
Sep 30, 2010
(6) TMQ0 option register 0 (TQ0OPT0)
The TQ0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TQ0CCS3
TQ0CCSm
0
1
TQ0CCRm register capture/compare selection
The TQ0CCSm bit setting is valid only in the free-running timer mode.
Compare register selected
Capture register selected
TQ0OPT0
TQ0CCS2 TQ0CCS1 TQ0CCS0 0 0 0 TQ0OVF
654321
After reset: 00H R/W Address: FFFFF545H
TQ0OVF
Set (1)
Reset (0)
TMQ0 overflow detection
• The TQ0OVF bit is set when the 16-bit counter count value overflows from
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
• An interrupt request signal (INTTQ0OV) is generated at the same time that the
TQ0OVF bit is set to 1. The INTTQ0OV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
• The TQ0OVF bit is not cleared even when the TQ0OVF bit or the TQ0OPT0
register are read when the TQ0OVF bit = 1.
• The TQ0OVF bit can be both read and written, but the TQ0OVF bit cannot be set
to 1 by software. Writing 1 has no influence on the operation of TMQ0.
Overflow occurred
TQ0OVF bit 0 written or TQ0CTL0.TQ0CE bit = 0
7 <0>
Cautions 1. Rewrite the TQ0CCS3 to TQ0CCS0 bits when the
TQ0CTL0.TQ0CE bit = 0. (The same value can be written
when the TQ0CE bit = 1.) If rewriting was mistakenly
performed, clear the TQ0CE bit to 0 and then set the bits
again.
2. Be sure to clear bits 1 to 3 to “0”.
Remark m = 0 to 3