Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 279 of 870
Sep 30, 2010
(1) 16-bit counter
This 16-bit counter can count internal clocks or external events.
The count value of this counter can be read by using the TQ0CNT register.
When the TQ0CTL0.TQ0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TQ0CNT register is read at this
time, 0000H is read.
Reset sets the TQ0CE bit to 0. Therefore, the 16-bit counter is set to FFFFH.
(2) CCR0 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TQ0CCR0 register is used as a compare register, the value written to the TQ0CCR0 register is
transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0
buffer register, a compare match interrupt request signal (INTTQ0CC0) is generated.
The CCR0 buffer register cannot be read or written directly.
The CCR0 buffer register is cleared to 0000H after reset, as the TQ0CCR0 register is cleared to 0000H.
(3) CCR1 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TQ0CCR1 register is used as a compare register, the value written to the TQ0CCR1 register is
transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1
buffer register, a compare match interrupt request signal (INTTQ0CC1) is generated.
The CCR1 buffer register cannot be read or written directly.
The CCR1 buffer register is cleared to 0000H after reset, as the TQ0CCR1 register is cleared to 0000H.
(4) CCR2 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TQ0CCR2 register is used as a compare register, the value written to the TQ0CCR2 register is
transferred to the CCR2 buffer register. When the count value of the 16-bit counter matches the value of the CCR2
buffer register, a compare match interrupt request signal (INTTQ0CC2) is generated.
The CCR2 buffer register cannot be read or written directly.
The CCR2 buffer register is cleared to 0000H after reset, as the TQ0CCR2 register is cleared to 0000H.
(5) CCR3 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TQ0CCR3 register is used as a compare register, the value written to the TQ0CCR3 register is
transferred to the CCR3 buffer register. When the count value of the 16-bit counter matches the value of the CCR3
buffer register, a compare match interrupt request signal (INTTQ0CC3) is generated.
The CCR3 buffer register cannot be read or written directly.
The CCR3 buffer register is cleared to 0000H after reset, as the TQ0CCR3 register is cleared to 0000H.
(6) Edge detector
This circuit detects the valid edges input to the TIQ00 and TIQ03 pins. No edge, rising edge, falling edge, or both
the rising and falling edges can be selected as the valid edge by using the TQ0IOC1 and TQ0IOC2 registers.
(7) Output controller
This circuit controls the output of the TOQ00 to TOQ03 pins. The output controller is controlled by the TQ0IOC0
register.
(8) Selector
This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can
be selected as the count clock.