Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 276 of 870
Sep 30, 2010
7.7 Cautions
(1) Capture operation
When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be
captured in the TPnCCR0 and TPnCCR1 registers if the capture trigger is input immediately after the TPnCE bit is
set to 1.
(a) Free-running timer mode
Count clock
0000H
FFFFH
TPnCE bit
TPnCCR0 register
FFFFH 0001H0000H
TIPn0 pin input
Capture
trigger input
16-bit counter
Sampling clock (f
XX )
Capture
trigger input
(b) Pulse width measurement mode
0000H
FFFFH
FFFFH 0002H0000H
Count clock
TPnCE bit
TPnCCR0 register
TIPn0 pin input
Capture
trigger input
16-bit counter
Sampling clock (f
XX)
Capture
trigger input