Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 273 of 870
Sep 30, 2010
7.5.8 Timer output operations
The following table shows the operations and output levels of the TOPn0 and TOPn1 pins.
Table 7-4. Timer Output Control in Each Mode
Operation Mode TOPn1 Pin TOPn0 Pin
Interval timer mode Square wave output
External event count mode Square wave output
−
External trigger pulse output mode External trigger pulse output
One-shot pulse output mode One-shot pulse output
PWM output mode PWM output
Square wave output
Free-running timer mode Square wave output (only when compare function is used)
Pulse width measurement mode
−
Remark n = 0 to 5
Table 7-5. Truth Table of TOPn0 and TOPn1 Pins Under Control of Timer Output Control Bits
TPnIOC0.TPnOLm Bit TPnIOC0.TPnOEm Bit TPnCTL0.TPnCE Bit Level of TOPnm Pin
0
×
Low-level output
0 Low-level output
0
1
1
Low level immediately before counting, high
level after counting is started
0
×
High-level output
0 High-level output
1
1
1
High level immediately before counting, low level
after counting is started
Remark n = 0 to 5
m = 0, 1