Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 267 of 870
Sep 30, 2010
7.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110)
In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set
to 1. Each time the valid edge input to the TIPnm pin has been detected, the count value of the 16-bit counter is stored in
the TPnCCRm register, and the 16-bit counter is cleared to 0000H.
The interval of the valid edge can be measured by reading the TPnCCRm register after a capture interrupt request
signal (INTTPnCCm) occurs.
Select either the TIPn0 or TIPn1 pin as the capture trigger input pin. Specify “No edge detected” by using the TPnIOC1
register for the unused pins.
Figure 7-34. Configuration in Pulse Width Measurement Mode
TPnCCR0 register
(capture)
TPnCE bit
TPnCCR1 register
(capture)
Edge
detector
Count
clock
selection
Edge
detector
Edge
detector
TIPn0 pin
(external
event count
input/capture
trigger input)
TIPn1 pin
(capture
trigger input)
Internal count clock
Clear
INTTPnOV signal
INTTPnCC0 signal
INTTPnCC1 signal
16-bit counter
Remark n = 0 to 5
m = 0, 1