Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)

R01UH0015EJ0300 Rev.3.00 Page 262 of 870

Sep 30, 2010

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Example when two capture registers are used (using overflow interrupt)

FFFFH

16-bit counter

0000H

TPnCE bit

INTTPnOV signal

TPnOVF bit

TPnOVF0 flag

Note

TIPn0 pin input

TPnCCR0 register

TPnOVF1 flag

Note

TIPn1 pin input

TPnCCR1 register

<1> <2> <5> <6><3> <4>

Note The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software.

<1> Read the TPnCCR0 register (setting of the default value of the TIPn0 pin input).

<2> Read the TPnCCR1 register (setting of the default value of the TIPn1 pin input).

<3> An overflow occurs. Set the TPnOVF0 and TPnOVF1 flags to 1 in the overflow interrupt servicing,

and clear the overflow flag to 0.

<4> Read the TPnCCR0 register.

Read the TPnOVF0 flag. If the TPnOVF0 flag is 1, clear it to 0.

Because the TPnOVF0 flag is 1, the pulse width can be calculated by (10000H + D

01 − D00).

<5> Read the TPnCCR1 register.

Read the TPnOVF1 flag. If the TPnOVF1 flag is 1, clear it to 0 (the TPnOVF0 flag is cleared in <4>,

and the TPnOVF1 flag remains 1).

Because the TPnOVF1 flag is 1, the pulse width can be calculated by (10000H + D

11 − D10)

(correct).

<6> Same as <3>