Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 259 of 870
Sep 30, 2010
(2) Operation timing in free-running timer mode
(a) Interval operation with compare register
When 16-bit timer/event counter P is used as an interval timer with the TPnCCRm register used as a compare
register, software processing is necessary for setting a comparison value to generate the next interrupt request
signal each time the INTTPnCCm signal has been detected.
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TOPn pin output
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
D 00 D 01 D 02 D 03 D 04 D 05
D 10
D 00
D 11
D 01
D 12
D 04
D 13
D 02
D 03
D 11 D 10 D 12 D 13 D 14
Interval period
(D
10 + 1)
Interval period
(10000H
+
D11 − D10)
Interval period
(10000H
+
D12 − D11)
Interval period
(10000H
+
D13 − D12)
Interval period
(D
00 + 1)
Interval period
(10000H +
D
01 − D 00 )
Interval period
(D
02 − D 01 )
Interval period
(10000H +
D
03 − D 02 )
Interval period
(10000H +
D
04 − D 03 )
When performing an interval operation in the free-running timer mode, two intervals can be set with one
channel.
To perform the interval operation, the value of the corresponding TPnCCRm register must be re-set in the
interrupt servicing that is executed when the INTTPnCCm signal is detected.
The set value for re-setting the TPnCCRm register can be calculated by the following expression, where “D
m” is
the interval period.
Compare register default value: D
m − 1
Value set to compare register second and subsequent time: Previous set value + D
m
(If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the
register.)
Remark n = 0 to 5
m = 0, 1