Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)

R01UH0015EJ0300 Rev.3.00 Page 256 of 870

Sep 30, 2010

Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)

TPnCE bit = 1

Read TPnOPT0 register

(check overflow flag).

TPnCTL0 register

(TPnCKS0 to TPnCKS2 bits)

TPnCTL1 register,

TPnIOC0 register,

TPnIOC2 register,

TPnOPT0 register,

TPnCCR0 register,

TPnCCR1 register

Initial setting of these registers

is performed before setting the

TPnCE bit to 1.

The TPnCKS0 to TPnCKS2 bits

can be set at the same time

when counting has been started

(TPnCE bit = 1).

START

Execute instruction to clear

TPnOVF bit (CLR TPnOVF).

<1> Count operation start flow

<2> Overflow flag clear flow

TPnCE bit = 0

Counter is initialized and

counting is stopped by

clearing TPnCE bit to 0.

STOP

<3> Count operation stop flow

TPnOVF bit = 1

YES

Remark n = 0 to 5