Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)

R01UH0015EJ0300 Rev.3.00 Page 255 of 870

Sep 30, 2010

(1) Operation flow in free-running timer mode

(a) When using capture/compare register as compare register

Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2)

FFFFH

16-bit counter

0000H

TPnCE bit

TPnCCR0 register

INTTPnCC0 signal

TOPn0 pin output

TPnCCR1 register

INTTPnCC1 signal

TOPn1 pin output

INTTPnOV signal

TPnOVF bit

Cleared to 0 by

CLR instruction

Set value changed

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

<1>

<2> <2> <2>

<3>

Set value changed

Remark n = 0 to 5