Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 254 of 870
Sep 30, 2010
Figure 7-31. Register Setting in Free-Running Timer Mode (2/2)
(d) TMPn I/O control register 1 (TPnIOC1)
0 0 0 0 0/1
TPnIOC1
Select valid edge
of TIPn0 pin input
Select valid edge
of TIPn1 pin input
0/1 0/1 0/1
TPnIS2 TPnIS1 TPnIS0TPnIS3
(e) TMPn I/O control register 2 (TPnIOC2)
0 0 0 0 0/1
TPnIOC2
Select valid edge of
external event count input
0/1 0 0
TPnEES0 TPnETS1 TPnETS0TPnEES1
(f) TMPn option register 0 (TPnOPT0)
0 0 0/1 0/1 0
TPnOPT0
Overflow flag
Specifies if TPnCCR0
register functions as
capture or compare register
Specifies if TPnCCR1
register functions as
capture or compare register
0 0 0/1
TPnCCS0 TPnOVFTPnCCS1
(g) TMPn counter read buffer register (TPnCNT)
The value of the 16-bit counter can be read by reading the TPnCNT register.
(h) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
These registers function as capture registers or compare registers depending on the setting of the
TPnOPT0.TPnCCSm bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIPnm pin is detected.
When the registers function as compare registers and when D
m is set to the TPnCCRm register, the
INTTPnCCm signal is generated when the counter reaches (D
m + 1), and the output signal of the TOPnm
pin is inverted.
Remark n = 0 to 5
m = 0, 1