Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 253 of 870
Sep 30, 2010
Figure 7-31. Register Setting in Free-Running Timer Mode (1/2)
(a) TMPn control register 0 (TPnCTL0)
0/1 0 0 0 0
TPnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1 0/1 0/1
TPnCKS2 TPnCKS1 TPnCKS0TPnCE
Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1
(b) TMPn control register 1 (TPnCTL1)
0 0 0/1 0 0
TPnCTL1
101
TPnMD2 TPnMD1 TPnMD0TPnEEETPnEST
1, 0, 1:
Free-running mode
0: Operate with count
clock selected by
TPnCKS0 to TPnCKS2 bits
1: Count on external
event count input signal
(c) TMPn I/O control register 0 (TPnIOC0)
0 0 0 0 0/1
TPnIOC0
0: Disable TOPn0 pin output
1: Enable TOPn0 pin output
Setting of output level with
operation of TOPn0 pin disabled
0: Low level
1: High level
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Setting of output level with
operation of TOPn1 pin disabled
0: Low level
1: High level
0/1 0/1 0/1
TPnOE1 TPnOL0 TPnOE0TPnOL1