Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)

R01UH0015EJ0300 Rev.3.00 Page 252 of 870

Sep 30, 2010

When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is

detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and a capture interrupt request signal

(INTTPnCCm) is generated.

The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it

generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and continues counting.

At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR

instruction by software.

Figure 7-30. Basic Timing in Free-Running Timer Mode (Capture Function)

FFFFH

16-bit counter

0000H

TPnCE bit

TIPn0 pin input

TPnCCR0 register

INTTPnCC0 signal

TIPn1 pin input

TPnCCR1 register

INTTPnCC1 signal

INTTPnOV signal

TPnOVF bit

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Remark n = 0 to 5