Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)

R01UH0015EJ0300 Rev.3.00 Page 251 of 870

Sep 30, 2010

When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOPn0 and

TOPn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TPnCCRm register,

a compare match interrupt request signal (INTTPnCCm) is generated, and the output signal of the TOPnm pin is inverted.

The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it

generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and continues counting.

At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR

instruction by software.

The TPnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at

that time, and compared with the count value.

Figure 7-29. Basic Timing in Free-Running Timer Mode (Compare Function)

FFFFH

16-bit counter

0000H

TPnCE bit

TPnCCR0 register

INTTPnCC0 signal

TOPn0 pin output

TPnCCR1 register

INTTPnCC1 signal

TOPn1 pin output

INTTPnOV signal

TPnOVF bit

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Remark n = 0 to 5

m = 0, 1