Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 248 of 870
Sep 30, 2010
(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is
FFFFH, the INTTPnCC1 signal is generated periodically.
Count clock
16-bit counter
TPnCE bit
TPnCCR0 register
TPnCCR1 register
INTTPnCC0 signal
INTTPnCC1 signal
TOPn1 pin output
D 00
0000H
D
00
0000H
D
00
0000H
D 00 − 1D 00 0000FFFF 0000 D 00 − 1D 00 00000001
Remark n = 0 to 5
To output a 100% waveform, set a value of (set value of TPnCCR0 register + 1) to the TPnCCR1 register. If the
set value of the TPnCCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
TPnCE bit
TPnCCR0 register
TPnCCR1 register
INTTPnCC0 signal
INTTPnCC1 signal
TOPn1 pin output
D 00
D 00 + 1
D
00
D 00 + 1
D
00
D 00 + 1
D 00 − 1D 00 0000FFFF 0000 D 00 − 1D 00 00000001
Remark n = 0 to 5