Datasheet
V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 242 of 870
Sep 30, 2010
Figure 7-25. Basic Timing in PWM Output Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
CCR0 buffer register
INTTPnCC0 signal
TOPn0 pin output
TPnCCR1 register
CCR1 buffer register
INTTPnCC1 signal
TOPn1 pin output
D
10
D
00
D
00
D
01
D
00
D
10
D
11
D
10
D
11
D
01
D
10
D
10
D
00
D
00
D
11
D
11
D
01
D
01
Active period
(D
10
)
Cycle
(D
00
+ 1)
Inactive period
(D
00
− D
10
+ 1)
When the TPnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
PWM waveform from the TOPn1 pin.
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TPnCCR1 register ) × Count clock cycle
Cycle = (Set value of TPnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1)
The PWM waveform can be changed by rewriting the TPnCCRm register while the counter is operating. The newly
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the
16-bit counter is cleared to 0000H.
The compare match interrupt request signal INTTPnCC0 is generated when the 16-bit counter counts next time after its
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches the value of
the CCR1 buffer register.
The value set to the TPnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
Remark n = 0 to 5, m = 0, 1