Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 239 of 870
Sep 30, 2010
(2) Operation timing in one-shot pulse output mode
(a) Note on rewriting TPnCCRm register
To change the set value of the TPnCCRm register to a smaller value, stop counting once, and then change the
set value.
If the value of the TPnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
TOPn0 pin output
(only when software
trigger is used)
D 10 D 11
D 00 D 01
D 00
D 10 D 10 D 10 D 01
D 11
D 00 D 00
Delay
(D
10 )
Delay
(D 10 )
Active level width
(D
00 − D 10 + 1)
Active level width
(D
00 − D 10 + 1)
Delay
(10000H + D
11 )
Active level width
(D
01 − D 11 + 1)
When the TPnCCR0 register is rewritten from D
00 to D01 and the TPnCCR1 register from D10 to D11 where D00
> D
01 and D10 > D11, if the TPnCCR1 register is rewritten when the count value of the 16-bit counter is greater
than D
11 and less than D10 and if the TPnCCR0 register is rewritten when the count value is greater than D01
and less than D
00, each set value is reflected as soon as the register has been rewritten and compared with the
count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value
matches D
11, the counter generates the INTTPnCC1 signal and asserts the TOPn1 pin. When the count value
matches D
01, the counter generates the INTTPnCC0 signal, deasserts the TOPn1 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the one-
shot pulse that is originally expected.
Remark n = 0 to 5
m = 0, 1