Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 238 of 870
Sep 30, 2010
(1) Operation flow in one-shot pulse output mode
Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
<1> <3>
TPnCE bit = 1
Register initial setting
TPnCTL0 register
(TPnCKS0 to TPnCKS2 bits)
TPnCTL1 register,
TPnIOC0 register,
TPnIOC2 register,
TPnCCR0 register,
TPnCCR1 register
Initial setting of these
registers is performed
before setting the
TPnCE bit to 1.
The TPnCKS0 to
TPnCKS2 bits can be
set at the same time
when counting has been
started (TPnCE bit = 1).
Trigger wait status
START
<1> Count operation start flow
TPnCE bit = 0
Count operation is
stopped
STOP
<3> Count operation stop flow
D10
D00
D11
D01
D00
D10
D11
<2>
D01
Setting of TPnCCR0, TPnCCR1
registers
As rewriting the
TPnCCRm register
immediately forwards
to the CCRm buffer
register, rewriting
immediately after
the generation of the
INTTPnCCR0 signal
is recommended.
<2> TPnCCR0, TPnCCR1 register setting change flow
Remark n = 0 to 5
m = 0, 1