Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 237 of 870
Sep 30, 2010
Figure 7-22. Register Setting for Operation in One-Shot Pulse Output Mode (2/2)
(d) TMPn I/O control register 2 (TPnIOC2)
00000
TPnIOC2
Select valid edge of
external trigger input
0 0/1 0/1
TPnEES0 TPnETS1 TPnETS0TPnEES1
(e) TMPn counter read buffer register (TPnCNT)
The value of the 16-bit counter can be read by reading the TPnCNT register.
(f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
If D
0 is set to the TPnCCR0 register and D1 to the TPnCCR1 register, the active level width and output
delay period of the one-shot pulse are as follows.
Active level width = (D
0 − D1 + 1) × Count clock cycle
Output delay period = (D1) × Count clock cycle
Caution One-shot pulses are not output even in the one-shot pulse output mode, if the value set
in the TPnCCR1 register is greater than that set in the TPnCCR0 register.
Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used
in the one-shot pulse output mode.
2. n = 0 to 5