Datasheet

V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 234 of 870
Sep 30, 2010
7.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011)
In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set
to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and outputs
a one-shot pulse from the TOPn1 pin.
Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger
is used, the TOPn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter
is stopped (waiting for a trigger).
Figure 7-20. Configuration in One-Shot Pulse Output Mode
CCR0 buffer register
TPnCE bit
TPnCCR0 register
TPnCCR1 register
CCR1 buffer register
Clear
Match signal
Match signal
INTTPnCC0 signal
Output
controller
(RS-FF)
TOPn1 pin
INTTPnCC1 signal
TOPn0 pin
Count clock
selection
Count start
control
Edge
detector
Software trigger
generation
TIPn0 pin
Transfer
Transfer
S
R
Output
controller
(RS-FF)
S
R
16-bit counter
Remark n = 0 to 5