Datasheet
V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 233 of 870
Sep 30, 2010
(e) Generation timing of compare match interrupt request signal (INTTPnCC1)
The timing of generation of the INTTPnCC1 signal in the external trigger pulse output mode differs from the
timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit
counter matches the value of the TPnCCR1 register.
Count clock
16-bit counter
TPnCCR1 register
TOPn1 pin output
INTTPnCC1 signal
D
1
D
1
− 2D
1
− 1D
1
D
1
+ 1 D
1
+ 2
Remark n = 0 to 5
Usually, the INTTPnCC1 signal is generated in synchronization with the next count up, after the count value of
the 16-bit counter matches the value of the TPnCCR1 register.
In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing
is changed to match the timing of changing the output signal of the TOPn1 pin.