Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 232 of 870
Sep 30, 2010
(d) Conflict between trigger detection and match with TPnCCR0 register
If the trigger is detected immediately after the INTTPnCC0 signal is generated, the 16-bit counter is cleared to
0000H and continues counting up. Therefore, the active period of the TOPn1 pin is extended by time from
generation of the INTTPnCC0 signal to trigger detection.
16-bit counter
TPnCCR0 register
INTTPnCC0 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
D0
D0 − 1D00000FFFF 0000 0000
Extended
Remark n = 0 to 5
If the trigger is detected immediately before the INTTPnCC0 signal is generated, the INTTPnCC0 signal is not
generated. The 16-bit counter is cleared to 0000H, the TOPn1 pin is asserted, and the counter continues
counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
TPnCCR0 register
INTTPnCC0 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
D 0
D 0 − 1D 0 0000FFFF 0000 0001
Shortened
Remark n = 0 to 5