Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 231 of 870
Sep 30, 2010
(c) Conflict between trigger detection and match with TPnCCR1 register
If the trigger is detected immediately after the INTTPnCC1 signal is generated, the 16-bit counter is
immediately cleared to 0000H, the output signal of the TOPn1 pin is asserted, and the counter continues
counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
D 1
D 1 − 10000FFFF 0000
Shortened
Remark n = 0 to 5
If the trigger is detected immediately before the INTTPnCC1 signal is generated, the INTTPnCC1 signal is not
generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOPn1
pin remains active. Consequently, the active period of the PWM waveform is extended.
16-bit counter
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
D1
D1 − 2D1 − 1D10000FFFF 0000 0001
Extended
Remark n = 0 to 5