Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)

R01UH0015EJ0300 Rev.3.00 Page 228 of 870

Sep 30, 2010

(2) External trigger pulse output mode operation timing

(a) Note on changing pulse width during operation

To change the PWM waveform while the counter is operating, write the TPnCCR1 register last.

Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC0 signal is detected.

FFFFH

16-bit counter

0000H

TPnCE bit

TPnCCR0 register

CCR0 buffer register

INTTPnCC0 signal

TPnCCR1 register

CCR1 buffer register

INTTPnCC1 signal

TOPn1 pin output

External trigger input

(TIPn0 pin input)

TOPn0 pin output

(only when software

trigger is used)