Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 227 of 870
Sep 30, 2010
Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
TPnCE bit = 1
Setting of TPnCCR0 register
Register initial setting
TPnCTL0 register
(TPnCKS0 to TPnCKS2 bits)
TPnCTL1 register,
TPnIOC0 register,
TPnIOC2 register,
TPnCCR0 register,
TPnCCR1 register
Initial setting of these
registers is performed
before setting the
TPnCE bit to 1.
The TPnCKS0 to
TPnCKS2 bits can be
set at the same time
when counting is
enabled (TPnCE bit = 1).
Trigger wait status
TPnCCR1 register write
processing is necessary
only when the set
cycle is changed.
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to
the CCRm buffer register.
START
Setting of TPnCCR1 register
<1> Count operation start flow
<2> TPnCCR0 and TPnCCR1 register
setting change flow
Setting of TPnCCR0 register
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to
the CCRm buffer register.
Setting of TPnCCR1 register
<4> TPnCCR0, TPnCCR1 register
setting change flow
Only writing of the TPnCCR1
register must be performed when
the set duty factor is changed.
When the counter is cleared after
setting, the value of the
TPnCCRm register is transferred
to the CCRm buffer register.
Setting of TPnCCR1 register
<3> TPnCCR0, TPnCCR1 register
setting change flow
TPnCE bit = 0
Counting is stopped.
STOP
<5> Count operation stop flow
Remark n = 0 to 5
m = 0, 1