Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 225 of 870
Sep 30, 2010
Figure 7-18. Register Setting for Operation in External Trigger Pulse Output Mode (2/2)
(d) TMPn I/O control register 2 (TPnIOC2)
00000
TPnIOC2
Select valid edge of
external trigger input
0 0/1 0/1
TPnEES0 TPnETS1 TPnETS0TPnEES1
(e) TMPn counter read buffer register (TPnCNT)
The value of the 16-bit counter can be read by reading the TPnCNT register.
(f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
If D
0 is set to the TPnCCR0 register and D1 to the TPnCCR1 register, the cycle and active level of the PWM
waveform are as follows.
Cycle = (D
0 + 1) × Count clock cycle
Active level width = D
1 × Count clock cycle
Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used
in the external trigger pulse output mode.
2. n = 0 to 5