Datasheet
V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 223 of 870
Sep 30, 2010
Figure 7-17. Basic Timing in External Trigger Pulse Output Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
TOPn0 pin output
(only when software
trigger is used)
D
1
D
0
D
0
D
1
D
1
D
1
D
1
D
0
D
0
D
0
Wait
for
trigger
Active level
width (D
1
)
Cycle (D
0
+ 1) Cycle (D
0
+ 1) Cycle (D
0
+ 1)
Active level
width (D
1
)
Active level
width (D
1
)
16-bit timer/event counter P waits for a trigger when the TPnCE bit is set to 1. When the trigger is generated, the 16-bit
counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOPn1
pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The
output of the TOPn0 pin is inverted. The TOPn1 pin outputs a high-level regardless of the status (high/low) when a trigger
occurs.)
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TPnCCR1 register) × Count clock cycle
Cycle = (Set value of TPnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1)
The compare match request signal INTTPnCC0 is generated when the 16-bit counter counts next time after its count
value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match
interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches the value of the
CCR1 buffer register.
The value set to the TPnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
The valid edge of an external trigger input signal, or setting the software trigger (TPnCTL1.TPnEST bit) to 1 is used as
the trigger.
Remark n = 0 to 5, m = 0, 1