Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 222 of 870
Sep 30, 2010
7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010)
In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit
is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting,
and outputs a PWM waveform from the TOPn1 pin.
Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software
trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOPn0 pin.
Figure 7-16. Configuration in External Trigger Pulse Output Mode
CCR0 buffer register
TPnCE bit
TPnCCR0 register
16-bit counter
TPnCCR1 register
CCR1 buffer register
Clear
Match signal
Match signal
INTTPnCC0 signal
Output
controller
(RS-FF)
Output
controller
TOPn1 pin
INTTPnCC1 signal
TOPn0 pin
Count
clock
selection
Count
start
control
Edge
detector
Software trigger
generation
TIPn0 pin
Transfer
Transfer
S
R
Remark n = 0 to 5