Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 221 of 870
Sep 30, 2010
If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the INTTPnCC1
signal is not generated because the count value of the 16-bit counter and the value of the TPnCCR1 register
do not match.
Figure 7-15. Timing Chart When D
01 < D11
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TPnCCR1 register
INTTPnCC1 signal
D 01
D 11
D 01 D 01 D 01 D 01
L
Remark n = 0 to 5