Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 220 of 870
Sep 30, 2010
(c) Operation of TPnCCR1 register
Figure 7-13. Configuration of TPnCCR1 Register
CCR0 buffer registerTPnCE bit
TPnCCR0 register
16-bit counter
TPnCCR1 register
CCR1 buffer register
Clear
Match signal
Match signal
INTTPnCC0 signal
INTTPnCC1 signal
Edge
detector
TIPn0 pin
Remark n = 0 to 5
If the set value of the TPnCCR1 register is smaller than the set value of the TPnCCR0 register, the
INTTPnCC1 signal is generated once per cycle.
Figure 7-14. Timing Chart When D
01 ≥ D11
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TPnCCR1 register
INTTPnCC1 signal
D 01
D 11
D 01
D 11 D 11 D 11 D 11
D 01 D 01 D 01
Remark n = 0 to 5