Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 216 of 870
Sep 30, 2010
Figure 7-11. Register Setting for Operation in External Event Count Mode (2/2)
(e) TMPn counter read buffer register (TPnCNT)
The count value of the 16-bit counter can be read by reading the TPnCNT register.
(f) TMPn capture/compare register 0 (TPnCCR0)
If D
0 is set to the TPnCCR0 register, the counter is cleared and a compare match interrupt request signal
(INTTPnCC0) is generated when the number of external event counts reaches (D
0 + 1).
(g) TMPn capture/compare register 1 (TPnCCR1)
Usually, the TPnCCR1 register is not used in the external event count mode. However, the set value of the
TPnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter
matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is
generated.
Therefore, mask the interrupt signal by using the interrupt mask flag (TPnCCMK1).
Caution When an external clock is used as the count clock, the external clock can be input only
from the TIPn0 pin. At this time, set the TPnIOC1.TPnIS1 and TPnIOC1.TPnIS0 bits to 00
(capture trigger input (TIPn0 pin): no edge detection).
Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used
in the external event count mode.
2. n = 0 to 5