Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 215 of 870
Sep 30, 2010
When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0 register is
transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, and a compare match interrupt request signal (INTTPnCC0) is generated.
The INTTPnCC0 signal is generated each time the valid edge of the external event count input has been detected (set
value of TPnCCR0 register + 1) times.
Figure 7-11. Register Setting for Operation in External Event Count Mode (1/2)
(a) TMPn control register 0 (TPnCTL0)
0/1 0 0 0 0
TPnCTL0
0: Stop counting
1: Enable counting
000
TPnCKS2 TPnCKS1 TPnCKS0TPnCE
(b) TMPn control register 1 (TPnCTL1)
00000
TPnCTL1
0, 0, 1:
External event count mode
001
TPnMD2 TPnMD1 TPnMD0TPnEEETPnEST
(c) TMPn I/O control register 0 (TPnIOC0)
00000
TPnIOC0
0: Disable TOPn0 pin output
0: Disable TOPn1 pin output
000
TPnOE1 TPnOL0 TPnOE0TPnOL1
(d) TMPn I/O control register 2 (TPnIOC2)
0 0 0 0 0/1
TPnIOC2
Select valid edge
of external event
count input
0/1 0 0
TPnEES0 TPnETS1 TPnETS0TPnEES1