Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 214 of 870
Sep 30, 2010
7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001)
In the external event count mode, the valid edge of the external event count input is counted when the
TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the specified number
of edges have been counted. The TOPn0 pin cannot be used.
Usually, the TPnCCR1 register is not used in the external event count mode.
Figure 7-9. Configuration in External Event Count Mode
16-bit counter
CCR0 buffer registerTPnCE bit
TPnCCR0 register
Edge
detector
Clear
Match signal
INTTPnCC0 signal
TIPn0 pin
(external event
count input)
Remark n = 0 to 5
Figure 7-10. Basic Timing in External Event Count Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
D0
D0 D0 D0
16-bit counter
TPnCCR0 register
INTTPnCC0 signal
External event
count input
(TIPn0 pin input)
D0
External
event
count
interval
(D
0 + 1)
D0 − 1D0 0000 0001
External
event
count
interval
(D
0 + 1)
External
event
count
interval
(D
0 + 1)
Remarks 1. This figure shows the basic timing when the rising edge is specified as the valid edge of the
external event count input.
2. n = 0 to 5