Datasheet

V850ES/JG3 CHAPTER 1 INTRODUCTION
R01UH0015EJ0300 Rev.3.00 Page 7 of 870
Sep 30, 2010
1.6 Function Block Configuration
1.6.1 Internal block diagram
NMI
TOQ00 to TOQ03
TIQ00 to TIQ03
RTP00 to RTP05
SOB0/SCL01
SIB0/SDA01
SCKB0
INTP0 to INTP7
INTC
16-bit timer/
counter Q:
1 ch
TOP00 to TOP50,
TOP01 to TOP51
TIP00 to TIP50,
TIP01 to TIP51
16-bit timer/
counter P:
6 ch
KR0 to KR7
RTO
CSIB1
DMAC
Watchdog
timer 2
Watch timer
Key return
function
Note 1
Note 2
RAM
ROM
PC
General-purpose
registers 32 bits × 32
Multiplier
16 × 16 → 32
ALU
System
registers
32-bit barrel
shifter
CPU
HLDRQ
HLDAK
ASTB
RD
WAIT
WR0, WR1
A0 to A21
AD0 to AD15
Ports
CG
Regulator
PLL
CLM
Internal
oscillator
PCM0 to PCM3
PCT0, PCT1, PCT4, PCT6
PDH0 to PDH5
PDL0 to PDL15
P90 to P915 P70 to P711
P50 to P55 P40 to P42 P30 to P39
P10, P11
P02 to P06
AV REF1
ANO0, ANO1
ANI0 to ANI11
AV
SS
AV REF0
ADTRG
CLKOUT
XT1
XT2
X1
X2
V DD
V SS
REGC
FLMD0
FLMD1
EV DD
EV SS
Instruction
queue
BCU
SOB1
SIB1
SCKB1
CSIB2
SOB2
SIB2
SCKB2
CSIB3
SOB3
SIB3
SCKB3
TXDA0/SOB4
RXDA0/SIB4
ASCKA0/SCKB4
TXDA2/SDA00
RXDA2/SCL00
CSIB0 I
2
C01
16-bit interval
timer M:
1 ch
UARTA0
CSIB4
UARTA2
I
2
C00
TXDA1/SDA02
RXDA1/SCL02
UARTA1
I
2
C02
DCU
DRST
DMS
DDI
DCK
DDO
A/D
converter
D/A
converter
RESET
LVI
Notes 1. 384/512/768/1024 KB (flash memory) (see Table 1-1)
2. 32/40/60 KB (see Table 1-1)