Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 212 of 870
Sep 30, 2010
If the set value of the TPnCCR1 register is less than the set value of the TPnCCR0 register, the INTTPnCC1
signal is generated once per cycle. At the same time, the output of the TOPn1 pin is inverted.
The TOPn1 pin outputs a square wave with the same cycle as that output by the TOPn0 pin.
Figure 7-7. Timing Chart When D
01 ≥ D11
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
TOPn0 pin output
INTTPnCC0 signal
TPnCCR1 register
TOPn1 pin output
INTTPnCC1 signal
D01
D11
D01
D11 D11 D11 D11
D01 D01 D01
Remark n = 0 to 5