Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 207 of 870
Sep 30, 2010
(1) Interval timer mode operation flow
Figure 7-5. Software Processing Flow in Interval Timer Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
TOPn0 pin output
INTTPnCC0 signal
D0
D0 D0 D0
<1> <2>
TPnCE bit = 1
TPnCE bit = 0
Register initial setting
TPnCTL0 register
(TPnCKS0 to TPnCKS2 bits)
TPnCTL1 register,
TPnIOC0 register,
TPnCCR0 register
Initial setting of these registers is performed
before setting the TPnCE bit to 1.
The TPnCKS0 to TPnCKS2 bits can be
set at the same time when counting has
been started (TPnCE bit = 1).
The counter is initialized and counting is
stopped by clearing the TPnCE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
Remark n = 0 to 5