Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)

R01UH0015EJ0300 Rev.3.00 Page 206 of 870

Sep 30, 2010

Figure 7-4. Register Setting for Interval Timer Mode Operation (2/2)

0 0 0 0 0/1

TPnIOC0

0: Disable TOPn0 pin output

1: Enable TOPn0 pin output

Setting of output level with

operation of TOPn0 pin disabled

0: Low level

1: High level

0: Disable TOPn1 pin output

1: Enable TOPn1 pin output

Setting of output level with

operation of TOPn1 pin disabled

0: Low level

1: High level

0/1 0/1 0/1

TPnOE1 TPnOL0 TPnOE0TPnOL1

(d) TMPn counter read buffer register (TPnCNT)

By reading the TPnCNT register, the count value of the 16-bit counter can be read.

(e) TMPn capture/compare register 0 (TPnCCR0)

If the TPnCCR0 register is set to D

0, the interval is as follows.

Interval = (D

0 + 1) × Count clock cycle

(f) TMPn capture/compare register 1 (TPnCCR1)

Usually, the TPnCCR1 register is not used in the interval timer mode. However, the set value of the

TPnCCR1 register is transferred to the CCR1 buffer register. A compare match interrupt request signal

(INTTPnCC1) is generated when the count value of the 16-bit counter matches the value of the CCR1

buffer register.

Therefore, mask the interrupt request by using the corresponding interrupt mask flag (TPnCCMK1).

Remarks 1. TMPn I/O control register 1 (TPnIOC1), TMPn I/O control register 2 (TPnIOC2), and TMPn

option register 0 (TPnOPT0) are not used in the interval timer mode.

2. n = 0 to 5